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[VHDL-FPGA-Verilog] ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现.rar

Description: ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现
Platform: | Size: 2664973 | Author: Ariesl | Hits:

[Technology Management] verilog与ISE

Description: verilog与ISE系列的，非常好
Platform: | Size: 7246820 | Author: win_hshiw | Hits:

[VHDL-FPGA-Verilog] VerilogHDLPLI

Description: Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,
Platform: | Size: 1024 | Author: 杨锐 | Hits:

[Other Embeded program] yunsuan-verilog

Description: 运算器的实现，即实验指导书中的实验一，文件中包含有原代码及端口设置（可变），用vrilog HDL编程，Xilinx ISE 6仿真，并在实际电路中得到实现．-operations for the realization of the experimental guidance of a book. document contains the original code and port settings (variable), with vrilog HDL programming, Xilinx ISE 6 simulation, and the actual circuit realization.
Platform: | Size: 1600512 | Author: 王越 | Hits:

[Other Embeded program] trafficLight-verilog

Description: 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
Platform: | Size: 1532928 | Author: 王越 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 自己编写的一个verilog时钟程序，在xilinx的ISE仿真通过-I have written a Verilog clock procedures, in Xilinx s ISE simulation through
Platform: | Size: 327680 | Author: lg | Hits:

[VHDL-FPGA-Verilog] ISE_chinese_user_guide

Description: Xilinx—ISE的中文使用说明，写的很简单，但对于入门者很实用。看过市面上很多Xilinx的书，发现很多都是在这本书的基础上稍加改写，。
Platform: | Size: 915456 | Author: joan | Hits:

[VHDL-FPGA-Verilog] ISE_assistant_design_tool

Description: Xilinx－ISE辅助设计工具的中文使用说明，包括IP核生成器，布局布线器，FPGA底层编辑器，时序分析器，集成化逻辑分析工具，功率分析工具-Xilinx-ISE-aided design tools for use in Chinese, including the IP core generator, layout router, FPGA Editor bottom, timing analyzer, integrated logic analysis tools, power analysis tools
Platform: | Size: 1589248 | Author: joan | Hits:

[VHDL-FPGA-Verilog] VGADIY

Description: 自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment
Platform: | Size: 416768 | Author: mcuxxq | Hits:

[VHDL-FPGA-Verilog] ADC_INTERFACE

Description: it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.
Platform: | Size: 6144 | Author: yasir ateeq | Hits:

[VHDL-FPGA-Verilog] ASYNCFIFO

Description: 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
Platform: | Size: 75776 | Author: Denny | Hits:

[VHDL-FPGA-Verilog] iic

Description: 一个verilog源代码，可用ISE等实现，功能为I2C接口标准建模。-A verilog source code, can be used, such as the realization of ISE, the functional model for the I2C interface standard.
Platform: | Size: 306176 | Author: PUDN_CHEN | Hits:

[VHDL-FPGA-Verilog] USB

Description: Verilog实现的USB程序，用ISE打开工程文件即可-Verilog implementation USB program, open the project file with the ISE can be
Platform: | Size: 140288 | Author: Roy | Hits:

[VHDL-FPGA-Verilog] Multiplier

Description: It s a design of a 4*4 multiplier based on Verilog, using Xilinx ISE.
Platform: | Size: 859136 | Author: wayne | Hits:

[VHDL-FPGA-Verilog] IDCT

Description: 用verilog HDL语言编写的IDCT程序，可以计算8*8的整形数矩阵，用ISE 9.1i编译通过-Using verilog HDL language of the IDCT program can calculate the number of 8* 8 matrix of plastic, with ISE 9.1i compiled by
Platform: | Size: 479232 | Author: 阿文 | Hits:

[VHDL-FPGA-Verilog] DES

Description: 在ISE平台上，利用Verilog编程实现数据的DES加密-In the ISE platform, using Verilog programming DES data encryption
Platform: | Size: 661504 | Author: ldh | Hits:

[VHDL-FPGA-Verilog] SwitchLed

Description: FPGA入门程序。适合编程初学者的学习。由开关控制LED灯的亮灭。ISE集成开发环境。Verilog HDL语言编写-FPGA entry procedures. Programming for beginners to learn. LED lights from the light switch control off. ISE Integrated Development Environment. Language Verilog HDL
Platform: | Size: 244736 | Author: 李海波 | Hits:

[VHDL-FPGA-Verilog] rax2

Description: rax2 fft implation the fft in verilog instance and in ise of xilinx it show how to istance fft core and the port used
Platform: | Size: 1024 | Author: LL | Hits:

[VHDL-FPGA-Verilog] Verilog-Design

Description: 包括三个文档: 1.基于Altera Quartus II 的模块化设计应用 2.基于Xilinx ISE的的模块化设计示例 3.模块化设计方法的设计流程-Consists of three documents: 1. Based on Altera Quartus II modular design applications 2. Xilinx ISE based on the modular design of Example 3. Modular Design for design process
Platform: | Size: 252928 | Author: Joseph | Hits:

[VHDL-FPGA-Verilog] ddr

Description: 基于FPGA的ddr控制器的设计与实现，verilog，ISE-FPGA-based controller design and implementation of ddr, verilog, ISE
Platform: | Size: 179200 | Author: 洪依 | Hits:
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